The ADK-500 is a high-end FPGA core board (system-on-module) built around the Pango Titan3 series PG3T500 FPGA, integrating 242,176 LUT6 logic units and 484,352 registers. The board carries 2GB of on-board DDR4 memory and two 256Mb QSPI flash devices, providing ample data cache and configuration storage, and routes 98 HPIO, 54 HDIO and 16 pairs of high-speed transceivers out through two high-speed board-to-board connectors. Its compact 80 mm x 60 mm footprint suits secondary development and product integration in embedded systems, high-speed data acquisition, industrial control and similar fields.
Specifications
Item
Specification
FPGA device
PG3T500-6IFFBG676
LUT6
242,176
Logic cells
529,760
Registers (FF)
484,352
Distributed RAM
6.3 Mb
DRM (36 Kb)
616
HRM (288 Kb)
68
APM
1,804
GPLL
4
PPLL
8
FPLL
7
PVT monitor
1
PCIe
Gen4 x8, 1
EMAC
2
HPIO
98
HDIO
54
Operating temperature
Industrial grade, -40 °C to +85 °C
DDR4 SDRAM
2x 1GB chips, 2GB total
QSPI flash
2x 32MB QSPI flash, for configuration files and user data
Clock
2x 200 MHz differential active clocks, reference clocks for the DDR4 controller and FPGA logic
