• ADK-9681 ADC FMC subcard front view: white shield cover, eight gold SSMC RF connectors on top and the FMC connector below
  • ADK-9681 connector end close-up: AD1, AD2, TRIGout, TRIGin, CLKout, CLKin, AD3 and AD4 gold SSMC connectors
  • ADK-9681 ADC FMC subcard angled view: shield cover, gold SSMC connectors on the left and the FMC connector on the right
  • ADK-9681 functional block diagram: four RF inputs to two GMS011 dual 14-bit 1000MSPS ADCs, HMC7044 JESD204B clock generator and the FMC VITA 57.1 high pin count connector
1 4

4-Channel 1GSPS 14-Bit ADC FMC Subcard ADK-9681

4-Channel 1GSPS 14-Bit ADC FMC Subcard ADK-9681

$7,886.00 USD
$7,886.00 USD
Sale Sold out
Shipping calculated at checkout.

The ADK-9681 is a JESD204B-interface FMC subcard built to the VITA 57.1 standard, providing four channels of 14-bit, 1GSPS ADC acquisition. Its ADC devices are GMS011 chips, fully compatible with the ADI AD9680-1000, with a full-power -3dB analog input bandwidth of up to 2GHz. The ADCs connect to the host FPGA through eight high-speed serial GTX transceiver lanes. The card is DC-coupled and supports analog signal input from DC to 2GHz. It is aimed at communications and wireless infrastructure, radar, broadband communications, millimeter-wave communications and automatic test equipment.

Overview

  • GMS011 ADC chip: 14-bit resolution, 2GHz full-power bandwidth, low-noise design
  • JESD204B high-speed serial interface: 8 GTX transceiver lanes, maximum line rate 10Gbps
  • HMC7044: ultra-low-jitter clock generator, ensuring synchronous acquisition accuracy
  • -40°C to +85°C wide operating temperature: industrial-grade reliability for harsh environments

Model Comparison

Model ADK-9681
Channels 4 channels
Sampling Rate 1 GSPS (per channel)
Resolution 14-bit
Analog Front-End Coupling DC coupled
Input Frequency Range DC to 2GHz
Input Amplitude Range 2 Vpp
Full-Power Analog Input Bandwidth (-3 dB) 2 GHz
Power Consumption 1.65 W per channel (@ 1 GSPS)
SNR 65 dBFS (@ fin = 170 MHz, -1 dBFS amplitude)
SFDR 82 dBFS (@ fin = 170 MHz, -1 dBFS amplitude)
ENOB 10.7 bit (@ fin = 170 MHz, -1 dBFS amplitude)
JESD204B Lane Configuration Mixed JESD204B lane configuration, maximum line rate 10Gbps
Clock Generator High-performance clock generator chip HMC7044
Local Oscillator 100 MHz local VCXO
External Clock Input 1 x external reference clock / external VCO clock input
Trigger Input 1 x trigger input signal, LVTTL (+3.3V) level standard
Trigger Output 1 x trigger output signal, LVTTL (+3.3V) level standard
Board Size 84.1mm x 69mm
Typical Power Consumption 8W
Power Supply +12V
Cooling Natural air cooling
Operating Temperature -40°C to +85°C
Storage Temperature -55°C to +125°C
Operating Humidity 5% to 95%, non-condensing

What's in the Box

  • FMC subcard x 1
View full details
Variant Variant total Quantity Price Variant total
ADK-9681ADK-9681
ADK-9681ADK-9681
$7,886.00/ea		 $0.00
$7,886.00/ea $0.00