{"product_id":"xilinx-zynq-7000-xc7z020-lmk04828-clock-synchronization-board-w104","title":"Xilinx Zynq-7000 XC7Z020 + TI LMK04828 Clock Synchronization Board ADK-W104","description":"\u003cp\u003eThe ADK-W104 is a high-performance, highly integrated clock synchronization board built around the Xilinx Zynq-7000 XC7Z020 SoC (dual-core ARM Cortex-A9 + FPGA) and the TI LMK04828 dual-PLL, ultra-low-jitter clock generator, providing up to 14 differential clock outputs through high-performance SMA connectors. Output frequencies are programmable from 0.1 Hz to 3 GHz with typical RMS jitter of 88 fs or less, and the board supports JESD204B Subclass 1 SYSREF generation and device clocking. A 122.88 MHz differential crystal and a 30.72 MHz TCXO provide the reference, and external reference input\/output supports cascaded, coherent multi-board synchronization. The board delivers a clean, precisely synchronized clock source for demanding RF and digital systems, speeding the path from prototype to production.\u003c\/p\u003e\u003ch3\u003eSpecifications\u003c\/h3\u003e\u003ctable\u003e\n\u003cthead\u003e\u003ctr\u003e\n\u003cth\u003eItem\u003c\/th\u003e\n\u003cth\u003eSpecification\u003c\/th\u003e\n\u003c\/tr\u003e\u003c\/thead\u003e\n\u003ctbody\u003e\n\u003ctr\u003e\u003cth colspan=\"2\"\u003eFPGA\u003c\/th\u003e\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eFPGA\u003c\/td\u003e\n\u003ctd\u003eXC7Z020-2CLG400I\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eCPU\u003c\/td\u003e\n\u003ctd\u003eDual-core ARM Cortex-A9 (up to 766 MHz)\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eSpeed grade\u003c\/td\u003e\n\u003ctd\u003e-2\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eTemperature grade\u003c\/td\u003e\n\u003ctd\u003eIndustrial, -40°C to +85°C\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eLogic cells\u003c\/td\u003e\n\u003ctd\u003e85K\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eLUTs\u003c\/td\u003e\n\u003ctd\u003e53,200\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eDSP slices\u003c\/td\u003e\n\u003ctd\u003e220\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eBlock RAM\u003c\/td\u003e\n\u003ctd\u003e4.9 Mb\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eFlip-flops\u003c\/td\u003e\n\u003ctd\u003e106,400\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\u003cth colspan=\"2\"\u003eClock and Synchronization\u003c\/th\u003e\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eClock generator\u003c\/td\u003e\n\u003ctd\u003eTI LMK04828 (dual PLL, ultra-low jitter)\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eDifferential outputs\u003c\/td\u003e\n\u003ctd\u003e14 channels (SMA-KHDC3 high-performance connectors)\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eOutput frequency range\u003c\/td\u003e\n\u003ctd\u003e0.1 Hz to 3 GHz (programmable)\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eRMS jitter (12 kHz to 20 MHz)\u003c\/td\u003e\n\u003ctd\u003e≤ 88 fs (typical)\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eJESD204B support\u003c\/td\u003e\n\u003ctd\u003eSubclass 1, SYSREF generation, device clock\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eReference oscillators\u003c\/td\u003e\n\u003ctd\u003e122.88 MHz differential crystal (OSCIN) + 30.72 MHz TCXO\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eMulti-board synchronization\u003c\/td\u003e\n\u003ctd\u003eExternal reference input\/output, cascaded coherent operation\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\u003cth colspan=\"2\"\u003eMemory and Interfaces\u003c\/th\u003e\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eDDR3 memory\u003c\/td\u003e\n\u003ctd\u003e2x 1GB DDR3 on the PS side, 2GB total, 32-bit bus\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eQSPI Flash\u003c\/td\u003e\n\u003ctd\u003e2x 32MB QSPI Flash, 64MB total, for FPGA user data storage\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eSD card slot\u003c\/td\u003e\n\u003ctd\u003eMicro SD, SDIO mode, for Linux boot\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eEthernet\u003c\/td\u003e\n\u003ctd\u003e1x PS-side Gigabit Ethernet interface\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eUART\u003c\/td\u003e\n\u003ctd\u003e5x PL-side UART interfaces via J30J connector\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eUSB UART\u003c\/td\u003e\n\u003ctd\u003e1x PS-side USB-UART interface, for serial debugging and data communication\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eJTAG\u003c\/td\u003e\n\u003ctd\u003e14-pin JTAG port, for FPGA program download and debugging\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eGPIO\u003c\/td\u003e\n\u003ctd\u003e4x PL GPIO interfaces\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eLED\u003c\/td\u003e\n\u003ctd\u003e4x PL LEDs\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\u003cth colspan=\"2\"\u003ePower and Dimensions\u003c\/th\u003e\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003ePower input\u003c\/td\u003e\n\u003ctd\u003e12V\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eDimensions\u003c\/td\u003e\n\u003ctd\u003e230 mm x 120.1 mm\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003c\/tbody\u003e\n\u003c\/table\u003e\u003ch3\u003eWhat’s in the box\u003c\/h3\u003e\u003cul\u003e\n\u003cli\u003eClock synchronization board x 1\u003c\/li\u003e\n\u003cli\u003eSD card x 1\u003c\/li\u003e\n\u003cli\u003ePower adapter x 1\u003c\/li\u003e\n\u003cli\u003ePower cord x 1\u003c\/li\u003e\n\u003c\/ul\u003e","brand":"AMD","offers":[{"title":"Default Title","offer_id":67937915732197,"sku":"ADK-W104","price":5633.0,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0856\/1511\/6517\/files\/adk-w104-clock-synchronization-board-top.jpg?v=1793409147","url":"https:\/\/adevkit.com\/products\/xilinx-zynq-7000-xc7z020-lmk04828-clock-synchronization-board-w104","provider":"Advanced DevKit","version":"1.0","type":"link"}