{"product_id":"amd-virtex-ultrascale-fpga-development-board-vu13g","title":"AMD Virtex UltraScale+ FPGA Development Board ADK-VU13G","description":"\u003cp\u003eThe ADK-VU13G is a high-end FPGA development and verification platform built around the AMD Virtex UltraScale+ XCVU13P FPGA (XCVU13P-2FHGB2104I), designed for the most demanding data processing, high-speed interconnect and compute acceleration challenges, and an ideal platform for researchers, algorithm engineers and system architects carrying out prototyping and product development. It combines 3,780K logic cells, 12,288 DSP slices delivering 38.3 TOP\/s of peak INT8 performance, 76 GTY transceivers at 28.21 Gbps, 20GB of DDR4 memory and 256MB of QSPI flash with two 200G QSFP-DD and seven 100G QSFP28 optical ports (1.1 Tbps of total network bandwidth), FMC+ and FMC HPC expansion and PCIe Gen3 x16. Its enhanced DSP core is optimised for fixed- and floating-point computation including INT8, meeting the needs of AI inference and compute-intensive applications such as network systems above 1 Tb\/s, machine learning, compute acceleration, test and measurement, and radar and early-warning systems. Application areas: compute acceleration, 5G base stations, wired communications, network acceleration, test and measurement, machine learning and AI, radar, and emulation and prototyping.\u003c\/p\u003e\u003ch3\u003eSpecifications\u003c\/h3\u003e\u003ctable\u003e\n\u003cthead\u003e\u003ctr\u003e\n\u003cth\u003eItem\u003c\/th\u003e\n\u003cth\u003eSpecification\u003c\/th\u003e\n\u003c\/tr\u003e\u003c\/thead\u003e\n\u003ctbody\u003e\n\u003ctr\u003e\u003ctd colspan=\"2\"\u003e\u003cstrong\u003eCore board\u003c\/strong\u003e\u003c\/td\u003e\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eFPGA device\u003c\/td\u003e\n\u003ctd\u003eXCVU13P-2FHGB2104I\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eOperating temperature\u003c\/td\u003e\n\u003ctd\u003eIndustrial grade, -40 °C to +85 °C\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eMemory\u003c\/td\u003e\n\u003ctd\u003e20GB DDR4\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eQSPI flash\u003c\/td\u003e\n\u003ctd\u003e256MB\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eSystem logic cells\u003c\/td\u003e\n\u003ctd\u003e3,780K\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eFlip-flops\u003c\/td\u003e\n\u003ctd\u003e3,456K\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eLook-up tables\u003c\/td\u003e\n\u003ctd\u003e1,728K\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eMax. distributed RAM\u003c\/td\u003e\n\u003ctd\u003e48.3 Mb\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eTotal Block RAM\u003c\/td\u003e\n\u003ctd\u003e94.5 Mb\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eUltraRAM\u003c\/td\u003e\n\u003ctd\u003e360.0 Mb\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eDSP slices\u003c\/td\u003e\n\u003ctd\u003e12,288\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003ePeak INT8 DSP\u003c\/td\u003e\n\u003ctd\u003e38.3 TOP\/s\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003ePCI Express\u003c\/td\u003e\n\u003ctd\u003ePCIe Gen3 x16\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e150G Interlaken\u003c\/td\u003e\n\u003ctd\u003e8\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e100G Ethernet MAC\/PCS\u003c\/td\u003e\n\u003ctd\u003e12\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eGTY transceivers\u003c\/td\u003e\n\u003ctd\u003e76x 28.21 Gbps\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eHP I\/O\u003c\/td\u003e\n\u003ctd\u003e377\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\u003ctd colspan=\"2\"\u003e\u003cstrong\u003eInterfaces and features\u003c\/strong\u003e\u003c\/td\u003e\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eQSFP-DD ports\u003c\/td\u003e\n\u003ctd\u003e2x QSFP-DD ports, 8 lanes each, 16 lanes total, connected to the FPGA GTY transceivers, up to 25 Gbps per lane\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eQSFP28 ports\u003c\/td\u003e\n\u003ctd\u003e7x QSFP28 ports, 4 lanes each, 28 lanes total, connected to the FPGA GTY transceivers, up to 25 Gbps per lane\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eFMC+ connector\u003c\/td\u003e\n\u003ctd\u003e1x standard FMC+ connector, for FMC+ and FMC modules (HDMI input\/output modules, binocular camera modules, high-speed AD modules, etc.)\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eFMC connector\u003c\/td\u003e\n\u003ctd\u003e1x standard FMC HPC expansion connector, for FMC daughter cards (HDMI input\/output modules, binocular camera modules, high-speed AD modules, etc.)\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eGigabit Ethernet\u003c\/td\u003e\n\u003ctd\u003e1x Gigabit Ethernet port, for Ethernet data exchange with a computer or other network equipment\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eSMA input\/output\u003c\/td\u003e\n\u003ctd\u003e9 pairs of SMA differential connectors to the FPGA high-speed transceiver pins, plus 1 differential clock and 1 trigger signal, for high-speed transceiver and differential-pair signal verification\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eUSB UART\u003c\/td\u003e\n\u003ctd\u003e1x UART-to-USB interface, for communication with a computer and debugging\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eMicro SD slot\u003c\/td\u003e\n\u003ctd\u003e1x Micro SD card slot, for operating-system images and file systems\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eJTAG\u003c\/td\u003e\n\u003ctd\u003e1x 14-pin 2.00mm standard JTAG port, for FPGA program download and debugging\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eDIP switch\u003c\/td\u003e\n\u003ctd\u003e4-position DIP switch, for simple input verification\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eLEDs\u003c\/td\u003e\n\u003ctd\u003e6 LEDs: on the core board, 1 user indicator and 1 DONE configuration indicator; on the baseboard, 2 user indicators and 2 serial-port indicators\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eButton\u003c\/td\u003e\n\u003ctd\u003e1x user button\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\u003ctd colspan=\"2\"\u003e\u003cstrong\u003ePower\u003c\/strong\u003e\u003c\/td\u003e\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003ePower supply\u003c\/td\u003e\n\u003ctd\u003e12V \/ 15A\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eInput voltage\u003c\/td\u003e\n\u003ctd\u003e+12V\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eInput current\u003c\/td\u003e\n\u003ctd\u003e15A maximum\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\u003ctd colspan=\"2\"\u003e\u003cstrong\u003eMechanical\u003c\/strong\u003e\u003c\/td\u003e\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eDimensions\u003c\/td\u003e\n\u003ctd\u003e210 mm x 255 mm\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003c\/tbody\u003e\n\u003c\/table\u003e\u003ch3\u003eWhat’s in the box\u003c\/h3\u003e\u003cul\u003e\n\u003cli\u003eFPGA development board x 1\u003c\/li\u003e\n\u003cli\u003eUSB downloader x 1\u003c\/li\u003e\n\u003cli\u003eMini USB cable x 1\u003c\/li\u003e\n\u003cli\u003eCooling fan x 1\u003c\/li\u003e\n\u003cli\u003eSMA cables x 6\u003c\/li\u003e\n\u003cli\u003eSMA elbows x 7\u003c\/li\u003e\n\u003cli\u003e12V power supply x 1\u003c\/li\u003e\n\u003cli\u003eSD card x 1\u003c\/li\u003e\n\u003c\/ul\u003e","brand":"AMD","offers":[{"title":"Default Title","offer_id":67937674100965,"sku":"ADK-VU13G","price":22531.0,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0856\/1511\/6517\/files\/adk-vu13g-virtex-ultrascale-fpga-board-top-view-with-fan.jpg?v=1793405953","url":"https:\/\/adevkit.com\/products\/amd-virtex-ultrascale-fpga-development-board-vu13g","provider":"Advanced DevKit","version":"1.0","type":"link"}